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Overview

HH 40NULP_ADC_SAR50M is a 14-bits resolution, 50MHz sample rate, differential input on HH 40nm LP Process. The internal ADC includes sample and hold circuit, a capacitive DAC, a comparator, logic control circuits and calibrate circuits.

 

Features

n 14bits resolution

n MAX Sampling rate: 50Msps

n SNDR: 75dB@50Msps, 5.078125MHz input signal

n Differential input

n Power Supply:

Analog power supply 1V ~ 1.2V

Digital power supply 1V~ 1.2V

n Power consumption of ADC core: 1mA@50Msps

n TA = -40°C ~ 125°C

n HH 40nm LP 1P6M Process

n Size: 307um*110um