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旋极星源的模拟IP涵盖了ADC\PLL\LDO\RTC\DCDC等，全部已在不同客户的多种制程产品得到验证，同时还能根据客户需求定制。可广泛应用于物联网、卫星导航等领域。
ULTRA Process Low Cost、Low Power 12-Bits 12.5Msps SAR ADC
ULP Process Low Power Bandgap Reference
ULP Process Ultra Low Power Bandgap Reference
ULP Process DCDC Bulk
ULP Process Low Power LDO Regulator
ULP Process Low Power LDO Capacitor Free Regulator
ULP Process Ultra Low Power LDO Regulator
ULP Process Ultra Low Power Capacitor Free LDO Regulator
ULP Process Ultra Low Power POR
ULP process Low Jitter Delta-sigma Fractional-N PLL
ULP process Ultra-low Power 32KHz Oscillator
ULP Process Selectable RC Oscillator
| 型号 | 简介 | 工艺 | ||
| SRCO | TSMC40ULP_SRCO is an IP version of a ultra low power RC on-chip oscillator. The oscillator provides a selectable clock (1MHz/2MHz/4MHz/8MHz/16MHz/24MHz/32MHz/64MHz) with digital calibration to minimize process variations. After fine-tuning the oscillator guarantees less than ±1.5% frequency variation from -40 to 100 degrees(All PVT corners). Fabricated in TSMC 40nm ULP process, this oscillator occupies an area of TBDµm×TBDµm. | |||
| OSC_32KHz | OSC_32KHz is an on-chip clock generator that generates low frequency oscillator clock, which includes starting circuit, current source circuit, charge-discharge circuit and automatic calibration circuit. After frequency calibration, the frequency accuracy can reach ±2% over a wide temperature range, and consumes ultra-low power. While generating 32KHz output clock, the static current which the whole OSC IP consumes, is as low as 95nA. | |||
| Low Jitter Delta-sigma Fractional-N PLL | This IP is a low jitter wideband frequency synthesizer which allows implementation of fractional-N or integer -N mode when used with an external reference frequency. The IP is based on TSMC 40nm ULP process. This IP can achieve the frequency output range of 25MHz~1600MHz, support automatic frequency calibration. It supports 3MHz to 100MHz input clock frequency range. | |||
| POR_ULP | T40NULP_POR_ULP is an IP version of ultra low power power on reset.The POR IP supports input power voltage from 1.8V to 3.6V. Various delay time of POR is provided. | |||
| LDO_ULP_CAPFR | T40NULP_LDO_ULP_CAPFR is an IP version of ultra low power LDO regulator without filter capacitor. The typical output voltage of the IP is 0.9V with low temperature coefficient and this voltage can be programmed from 0.81V to 0.99V. The LDO IP supports input power voltage from 1.8V to 3.6V. | |||
| LDO_ULP_CAP | T40NULP_LDO_ULP_CAP is an IP version of ultra low power LDO regulator with 2.2uF filter capacitor. The typical output voltage of the IP is 0.9V with low temperature coefficient and this voltage can be programmed from 0.81V to 0.99V. The LDO IP supports input power voltage from 1.8V to 3.6V. | |||
| LDO_LP_CAPFR | T40NULP_LDO_LP_CAPFR is an IP version of low power LDO regulator without filter capacitor. The typical output voltage of the IP is 0.9V with low temperature coefficient and this voltage can be programmed from 0.81V to 1.21V. The LDO IP supports input power voltage from 1.8V to 3.6V. | |||
| LDO_LP_CAP | T40NULP_LDO_LP_CAP is an IP version of low power LDO regulator with 2.2uF filter capacitor. The typical output voltage of the IP is 0.9V with low temperature coefficient and this voltage can be programmed from 0.81V to 1.21V. The LDO IP supports input power voltage from 1.8V to 3.6V. | |||
| DCDC_Bulk | T40NULP_DCDC_Bulk is an IP version of low power and high efficiency PWM step-down DC/DC converter IP with fast transient response and accurate regulation. Both the main (P-Channel MOSFET) and synchronous (N-Channel MOSFET) switches are integrated. It works with PWM mode. It can apply to on-chip digital circuits which need fast respond power supply. | |||
| BGR_ULP | T40NULP_BGR_ULP is an IP version of ultra low power reference. Its quiescent is 60nA. The typical reference voltage of the IP is 0.9V with low temperature coefficient and this voltage can be programmed from 0.82V to 0.97V.This IP can be suitably used for ultra low power regulator. | |||
| BGR_LP | T40NULP_BGR_LP is an IP version of low power bandgap reference. Its PSRR is -70dB. The typical reference voltage of the IP is 0.75V with low temperature coefficient and this voltage can be programmed from 0.67V to 0.82V.This IP can be suitably used for low power regulator. | |||
| ADC_SAR12B5M | T40NULP_ADC_SAR12P5M is a 12-bits resolution, 12.5MHz sample rate, differential or single ended multi-channel input on TSMC 40nm ULP Process. The internal ADC includes sample and hold circuit, a capacitive DAC, a comparator, and logic control circuits. | |||
| ULP Process Low Power Bandgap Reference | ||||
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