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旋极星源自主研发了超低功耗模拟IP,涵盖了电源管理、数模转换、时钟管理等。ADC\PLL\RTC\LDO\DCDC\POR多种模拟IP全部已在不同客户的多种制程产品得到验证以低成本、低功耗、高性能有效助力客户在物联网(IoT)、可穿戴产品、工业控制、智慧城市、汽车电子等市场中提升竞争力。
型号 | 简介 | 工艺 | ||
HH 40nm LP Process Operational Amplifier | HH40NLP_OPA is Operational Amplifier which Supports standalone mode, buffer mode, PGA mode , LPF mode and comparator mode.The input power voltage of OPA is from 1.8V to 3.6V. | HH40NLP | ||
ULP Process Ultra Low Power POR | T40NULP_POR_ULP is an IP version of ultra low power power on reset.The POR IP supports input power voltage from 0.8V to 1.1V. Various delay time of POR is provided. | T40NULP | ||
ULP Process Ultra Low Power POR | T40NULP_POR_ULP is an IP version of ultra low power power on reset.The POR IP supports input power voltage from 0.8V to 1.1V. Various delay time of POR is provided. | T40NULP | ||
ULP Process Ultra Low Power POR | T40NULP_POR_ULP is an IP version of ultra low power power on reset.The POR IP supports input power voltage from 2.8V to 3.6V. Various delay time of POR is provided. | T40NULP | ||
ULP Process Ultra Low Power POR_HA | T40NULP_POR_ULP is an IP version of ultra low power power on reset.The POR IP supports input power voltage from 2.8V to 3.6V. Various delay time of POR is provided. | T40NULP | ||
ULP process Ultra-low Power 32.768KHz Oscillator | OSC_32.768KHz is an on-chip clock generator that generates low frequency oscillator clock, which includes starting circuit, current source circuit, charge-discharge circuit and automatic calibration circuit. | TSMC 40nm ULP | ||
ULP ProcessSelectable RC Oscillator | TSMC 40nm ULP selectable RC oscillator is an IP version of a ultra low power RC on-chip oscillator. It provides a selectable clock(1MHz/2MHz/4MHz/8MHz/16MHz/24MHz/32MHz/64MHz) with digital calibration to minimize process variations. After fine-tuning the oscillator guarantees less than ±3% frequency variation from -40 to 125 degrees(All PVT corners). Fabricated in TSMC 40nm ULP process, this oscillator occupies an area of 0.025mm2. | T40nm ULP | ||
ULP Process Ultra Low Power Capacitor Free LDO Regulator | T40NULP_LDO_ULP_CAPFR is an IP version of ultra low power LDO regulator without filter capacitor. The typical output voltage of the IP is 0.9V with low temperature coefficient and this voltage can be programmed from 0.825V to 0.984V. The LDO IP supports input power voltage from 1.8V to 3.6V. | T40NULP | ||
ULP Process Low Power LDO Capacitor Free Regulator | T40NULP_LDO_LP_CAPFR is an IP version of low power LDO regulator without filter capacitor. The typical output voltage of the IP is 0.9V with low temperature coefficient and this voltage can be programmed from 0.81V to 1.21V. The LDO IP supports input power voltage from 1.8V to 3.6V. | T40NULP | ||
ULP Process Low Power LDO Regulator | T40NULP_LDO_LP_CAP is an IP version of low power LDO regulator, which can drive from 2.2uF to 4.7uF filter capacitor. The typical output voltage of the IP is 0.9V with low temperature coefficient and this voltage can be programmed from 0.79V to 1.28V. The LDO IP supports input power voltage from 1.8V to 3.6V. | T40NULP | ||
ULP Process Ultra Low Power Bandgap Reference | T40NULP_BGR_ULP is an IP version of ultra low power reference. Its quiescent is 60nA. The typical reference voltage of the IP is 0.9V with low temperature coefficient and this voltage can be programmed from 0.82V to 0.97V.This IP can be suitably used for ultra low power regulator. | T40NULP | ||
ULP Process Low Power Bandgap Reference | T40NULP_BGR_LP is an IP version of low power bandgap reference. Its PSRR is -70dB. The typical reference voltage of the IP is 0.75V with low temperature coefficient and this voltage can be programmed from 0.67V to 0.82V.This IP can be suitably used for low power regulator. | T40NULP | ||
ULP Process DCDC_A Bulk | T40NULP_DCDC_A Bulk is an IP version oflow power and high efficiency PWM step-down DC/DC converterIP with fast transient responseand accurate regulation.Both the main(P-Channel MOSFET)and synchronous(N-ChannelMOSFET)switches are integrated.it works with PWM mode.lt can apply to on-chip digital circuits which need fast respond power supply. | T40NULP | ||
ULP Process Low Jitter Delta-sigma Fractional-N PLL | This IP is a low jitter wideband frequency synthesizer which allows implementation of fractional-Nor integer -N mode when used with an external reference frequency.The IP is based on TSMC 40nmULP process. | T40nmULP | ||
ULP Process Low Cost,Low Power 12-Bits 2Msps SAR ADC | T40NULP_ADC_SAR2M is a 12-bits resolution, 2MHz sample rate, differential input on TSMC 40nmULP Process. The internal ADC includes sample and hold circuit, a capacitive DAc, a comparator, andlogic control circuits. | T40NULP | ||
LP Process Low Cost,Low Power 12-Bits 320Msps SAR ADC | 40NULP_ADC_SAR320M is a 12-bits resolution, 320MHz sample rate, differential input on UMC40nm LP Process. The internal ADC includes sample and hold circuit, a capacitive DAC, acomparator,and logic control circuits. | 40NULP | ||
LP Process Low Cost,Low Power 12-Bits160Msps SAR ADC | 40NULP_ADC_SAR12B160M is a 12-bits resolution, 160MHz sample rate SAR ADC IP on UMC40nm LP Process. The SAR ADC IP includes sample and hold circuits, capacitive DAC, comparatorinternal compare clock and logic control circuits, supports differential or single ended inputsignals | 40NULP | ||
ULP Process Low Cost,Low Power 12-Bits100Msps SAR ADC | T40NULP_ADC_SAR12B100M is a 12-bits resolution, 100MHz sample rate SAR ADC IP On TSMC40nm ULP Process. The SAR ADC IP includes sample and hold circuits, capacitive DAC, comparatorinternal compare clock and logic control circuits, supports differential or single ended input signals. | T40NULP | ||
LP Process Low Cost,Low Power 14-Bits 50Msps SAR ADC | HH 40NULP_ADC_SAR50M is a 14-bits resolution, 50MHz sample rate, differential input on HH 40nm LP Process. The internal ADC includes sample and hold circuit, a capacitive DAC, a comparator, logic control circuits and calibrate circuits. | HH 40NULP |
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